1. Field of the Invention
The present invention relates generally to a multigate field effect transistor and a process thereof, and more specifically to a multigate field effect transistor and a process thereof that forms voids in a dielectric layer between fin-shaped structures.
2. Description of the Prior Art
With increasing miniaturization of semiconductor devices, various multi-gate MOSFET devices have been developed. The multi-gate MOSFET is advantageous for the following reasons. First, manufacturing processes of multi-gate MOSFET devices can be integrated into traditional logic device processes, and thus are more compatible. In addition, since the three-dimensional structure of the multi-gate MOSFET increases the overlapped area between the gate and the substrate, the channel region is controlled more effectively. This therefore reduces drain-induced barrier lowering (DIBL) effect and short channel effect. Moreover, the channel region is longer for the same gate length. Therefore, the current between the source and the drain is increased.
A multigate field effect transistor component includes fin-shaped structures on a substrate, and a gate structure and a source/drain on each of the fin-shaped structures, to form multigate field effect transistors having multi gate channels. However, assizes of multigate field effect transistors shrink, the parasitic capacitances between each of the fin-shaped structures become large and degrade electrical performances of the multigate field effect transistors.